1. Field of the Invention
The present invention relates to an operation estimation technique for a program expressed in a simulation model, and more particularly, to a method and an article of manufacture for estimating a memory access conflict.
2. Description of Related Art
In recent years, modeling and simulation using MATLAB®/Simulink®, the Unified Modeling Language (UML), the Systems Modeling Language (SysML) or the like are frequently performed in the design process of embedded system program development.
On the other hand, developed programs are executed by hardware in predetermined computers, and performances are tested. Since multicore CPUs are recently coming into common use, the need to simulate computers having a multicore CPU is increasing also in consideration of an improvement in speed due to parallel execution.
However, in computers having a multicore CPU, individual cores access a memory via buses, which causes the problem of memory access conflict, which exerts an influence on program execution time.
Design flexibility is remarkably high at the early developing stage of embedded system design. For example, there are 216 patterns for assigning three software components to two cores and three memory areas, and thus, it is important to exclude inappropriate combinations at rough measurement before entering a detailed design stage.
However, existing performance evaluation methods are not suitable for measuring memory access conflict at a system architecture design phase.
For example, it is so difficult for an abstract mathematic technique, such as a queuing network model, to describe the behavior of an application, such as state transition that it cannot generate execution time per execution, and thus, it is used mainly for a statistical purpose.
Another technique, such as a fine-grained step simulation technique, for example, SystemC and an instruction set simulator (ISS), needs accurate memory access timing, and thus has the problems of high cost to collect such data at an early design stage and taking too much time for simulation.
A yet another technique uses an instruction level trace. However, with this technique, measurement itself interferes with the system performance. In addition to this, enormous time needed for simulation.
Japanese Unexamined Patent Application Publication No. 8-339388 discloses a logical simulation method in a multiprocessor system, and in particular, to a method for accessing the same memory area from individual processors, in which a logical simulation and a software simulation are simultaneously operated, and the result of the logical simulation and the result of the software simulation are compared at any timing, where processor-specific read and write areas and a shared write area for all the processors are provided. A read instruction is used for a processor to read from the processor-specific read and write areas, and a write instruction is used for a processor to write to the processor-specific read and write areas and to the shared write area for all the processors so that processor conflict testing is performed using the writing from the individual processors to the write area shared by all the processors.
An object of Japanese Unexamined Patent Application Publication No. 2003-15965 is to provide a test method for automatically generating, in a symmetric multiprocessor that shares a memory, an instruction sequence for generating accesses to the memory at the same timing from a plurality of processors. It discloses a test program including a test-environment setting process, an instruction simulator for generating an expected value, a process of generating an execution trace of test instruction sequence, a result comparing process, a test-instruction-coverage-information storing process, and a test-instruction-sequence generating process, in which test instruction sequences are generated in parallel for the individual processors; the kinds, addresses, and the estimated numbers of executed instruction cycles of issued memory accesses are stored in coverage information. The coverage information is referred to when an instruction is generated from another processor. Test instructions corresponding to the number of the generated execution instruction cycles of the processor are selected, and a test instruction sequence in which accesses to a memory having the same address from the plurality of processors conflict is generated.
Japanese Unexamined Patent Application Publication No. 2007-102509 relates to an arbiter capable of reducing the latency of a bus master, in which when an interface receives a reservation request for accessing a memory of a second bus master from a first bus master, and when a control unit detects that the result of subtracting the bus band of a data bus that is currently used by a bus master of which the access reservation request is most recently permitted from the bus band of a data bus that is currently used by the second bus master is larger than the result of subtracting a bus band corresponding to the data bus reserved by the most recently permitted bus master from the maximum bus band of the data bus, an access reservation request from a bus master other than a bus master for which an access request has already been permitted is not permitted.
Mudge, T. N., Hayes, J. P., Buzzard, G. D. & Winsor, D.C. “Analysis of Multiple-Bus Interconnection Networks”, Journal of Parallel and Distributed Computing, 1986, 3, 328-343 discloses approximation in which memory accesses are at random, uniform, and independent among processors, and solving an algebraic equation for calculating a bandwidth utilization factor U* including both a new memory access and latency (retransmission) due to bus arbitration using a simple iteration method. However, the technology disclosed in this literature can be used for analyzing the entire memory bandwidth on a symmetric multiprocessor system but cannot be used either on a heterogeneous multiprocessor system or for analyzing a memory bandwidth at an application level.